What Is a Field Effect Transistor? How FETs Work

Field-effect transistors (FETs) use electric fields to modulate the amount of current flowing through a semiconductor channel. The electric field created by a FET gate alters the conductivity of its channel, thereby allowing a lightly loaded gate input to control a separate current path. Two common FET types are Junction FETs (JFETs) and Metal-Oxide-Semiconductor FETs (MOSFETs). Although they create the gate electric field using different methods, they both share the same fundamental approach to understanding their operation: the relationship between the voltage applied to the gate relative to the source (VGS), the electric field produced by the gate, the conductance of the channel, and finally, the resulting drain current.

VGS is relative to the source; however, additional limits are imposed on the drain current by the external circuit and operating region.

JFET or MOSFET classifies the type of gate construction, while N-channel or P-channel describes the carrier type and polarity; enhancement or depletion describes how the channel behaves at or near zero bias.

While FETs have high input impedance, that does not eliminate leakage or transient charging of the gate.

In the case of a real MOSFET, VGS(th) marks the beginning of conduction under defined conditions; it is not necessarily the same as a universal “fully on” gate voltage.

What Is a Field-Effect Transistor?

The field-effect transistor uses an electric field from the gate electrode to alter the conductance of a semiconductor channel that lies between the source and drain terminals of the transistor. A FET is commonly described as unipolar because normal channel conduction is dominated by one charge carrier type.

The source and drain form the main current path, and the gate is the controlling terminal that influences how much drain current a circuit can produce by modifying the conductance of the channel with respect to the gate-to-source voltage (VGS).

An early patent application for a field-effect concept was filed by Julius Edgar Lilienfeld in 1925. In 1959, the first successfully manufactured insulated-gate MOS field-effect transistor was produced by Atalla and Kahng at Bell Labs.

How Does the Gate Control the Channel?

The gate does not feed the drain current of a field-effect transistor. Instead, the VGS voltage determines the electric field produced in or around the semiconductor material. The VGS voltage does not act as an additional power supply.

The gate voltage produces an electric field that alters the distribution of mobile charge carriers within the channel of the field-effect transistor, thus changing the channel’s conductance and the amount of drain current that the circuit surrounding the field-effect transistor may produce.

The depletion region of a JFET expands or contracts due to the reverse bias across the gate-channel junction. The increase in the depletion region results in a narrowing of the conducting path of the channel, and an increase in the resistance of the channel.

In the case of a MOSFET, there is an insulating oxide layer between the gate electrode and the semiconductor underneath it. The application of gate voltage creates an electric field across the insulating layer, changing the surface charge state of the semiconductor, thus forming or modifying a conductive channel on the surface of the semiconductor. In both cases, the channel does not behave as an ideal wire when “on.” In the case of analog operation, the conductance can vary continuously, while the on state of the device still has a finite value of resistance in switching operation.

Drain current cannot be determined by the gate voltage alone. In addition to VGS, the drain current is also subject to all of the factors mentioned above, including supply voltage, load resistance, source potential, operating temperature, and operating region.

What Do the Gate, Source, Drain, and Body Do?

The gate, source, drain, and body are defined based on their electrical functions instead of merely their physical locations. A schematic drawing of a FET generally shows the gate, source, and drain, while a MOSFET model may also expose a body or bulk terminal.

The internal structure of many MOSFET packages ties together the body and source, thereby placing an intrinsic body diode between the source and drain that affects the reverse current characteristics of the MOSFET, as well as the forward voltage and reverse recovery characteristics of the intrinsic diode when they come into play inside a circuit.

Just because two different schematic labels look similar doesn’t mean that they will have the same physical pin arrangement. Similar schematic symbols can correspond to different packages and pin arrangements, which means that to properly wire a circuit or verify the PCB footprint, you need to refer to the pin configuration and package drawing found in the datasheet.

Does High Input Impedance Mean the Gate Draws No Current?

No. The high input impedance simply means the gate lightly loads the previous stage; it does not mean that the gate will draw no current under any condition.

When the DC bias is established on the MOSFET, the insulating gate blocks most continuous gate current, but real devices still have specified leakage current. When the gate voltage changes, the gate capacitances will either charge or discharge, and accordingly there can be a substantial transient current flowing into or out of the gate for a short time. The settled current flowing into or out of the gate will be low in comparison to the transient current flowing into or out of the gate. The high input impedance of a JFET is not due to an insulating oxide; it is due to the reverse bias of the gate-channel PN junction of the JFET, which substantially reduces the flow of steady gate current.

What Are the Main Types of FETs?

There are three major classifications of FETs along three axes: JFET and MOSFET refer to the structure of the gate; N-channel FETs and P-channel FETs refer to channel polarity and carrier type; enhancement-mode and depletion-mode FETs refer to the behavior of their conduction channels at or near zero-bias conditions.

When an enhancement-mode MOSFET (E-MOS) is placed in a near-zero Gate-to-Source (VGS) voltage bias condition, the FET is generally considered to be in an “off” state until sufficient gate-to-source voltage is applied to form or strengthen the channel path (the conductive path between Source and Drain). The term “Depletion Mode” is used to define a FET type that conducts at roughly “zero” (VGS) gate-source-bias conditions, with the most commonly used example being a JFET, a type of depletion-mode (i.e. normally-on) FET. Depletion-mode MOSFETs also exist. While these are all classes of FETs, each class of FET has different characteristics related to device behavior, voltage, current and frequency response; therefore, the labels “E-MOS” and “JFET” are not synonymous with the meaning of “FET.”

Beyond JFETs and MOSFETs, additional specialized FET structures include MESFETs (Metal-Semiconductor Field-Effect Transistors) and HEMTs (High Electron Mobility Transistors) that are used for high-frequency/high-power applications, FinFETs (Fin Field-Effect Transistors) for high-density integrated logic circuits and OFETs (Organic Field-Effect Transistors) utilized in organic electronics.

How Do FET Operating Regions Change Their Behavior?

Each of these operating-region names depicts how the Drain Current of a FET responds to VGS and VDS (i.e., Drain-Source Voltage); however, the exact boundaries of these operating regions will differ depending on the family of FET that is used. A simplified illustration of first-order Cutoff, Linear and Saturation Boundary regions of an N-Channel E-MOS FET is provided below.

One common misconception concerning terminology is that when referring to MOSFET “saturation”, this actually refers to the region of operation that behaves like a current source (as opposed to BJT terminology, which refers to a hard-on switch state). Some power MOSFET application notes will refer to “linear mode” as being equivalent to saturation when used in a “pass device” configuration. It is important to read the actual VGS/VDS conditions stated in the application note as opposed to relying on the labeling of “linear mode”.

The conditions presented are approximations to first order and are not intended to be used in place of a real FET datasheet. This means that actual performance can change based on temperature, process variation, channel-length effects and the safe operating area (SOA).

Which FET Datasheet Parameters Matter?

The expectation should not be for a FET article to represent a single threshold, gate voltage, drain voltage, current, or switching-speed range that would apply to every family member of the FET. Each of these parameters differs significantly depending on the application and device family of the FET (small-signal JFET, low-voltage silicon MOSFET, high-voltage MOSFET, SiC devices, and integrated transistors).

RDS(on) and VGS max are two numbers that will very likely be compared across parts without consideration of their respective test conditions. For example, the RDS(on) value for Infineon’s IRLZ44N, one of the more common logic-level power MOSFETs, indicates an on-resistance of approximately 22 mΩ max, but this value is only correct if the MOSFET is driven at its specification for VGS (10 V) and its stated junction temperature. If the MOSFET is driven with a 5 V gate or operated at a higher junction temperature, the RDS(on) will increase above the headline value. Additionally, while the absolute max rating for VGS on the IRLZ44N is ±16 V, this level is well above the 5 V gate-drive condition used for a specified low RDS(on) value. Hence, this maximum rating for VGS exists separately from the VGS(th) rating. Although a FET can be driven to voltages greater than the VGS(th) threshold, if you exceed ±16 V VGS, there is a risk of damaging the gate oxide, even though the channel will still conduct normally at lower gate voltages.

VGS(th) can also be misinterpreted easily. While crossing the VGS(th) threshold indicates the start of the turn-on process, the gate-charge curve shows that as the device approaches the intended gate-drive voltage, additional charge is required through the Miller region to reach the low RDS(on) condition specified for switching.

In addition to RDS(on) and VGS(max), the dynamic parameters associated with FETs also depend on their respective test conditions (Ciss, Coss, Crss, and Qg). Hence, it is necessary to compare devices at relevant voltage, current, frequency, and temperature rather than relying solely on a headline number from a manufacturer.

What Are Field-Effect Transistors Used For?

The application for a field-effect transistor is determined by the biasing of the circuit and the type of the device. A single family of FETs can support switching, amplification, buffering, control of current, or resistance-like behavior, but the relevant parameters differ between these applications.

What Are the Advantages and Limitations of FETs?

FET vs BJT: How Are They Different?

A FET is typically thought of as a Voltage Controlled Device since it is the voltage on the gate (VGS) that causes the electric field to alter the conductance of the channel. A bipolar junction transistor (BJT) operates through base-emitter bias and base current supporting the collector current. As such, these two types of devices use different input and carrier control models.

FETs have generally higher input impedances than BJTs, especially with insulated gates, while BJTs require continuous bias current to operate normally. Both of these types of devices have constraints related to dynamic, thermal, gain, operating-region, polarity, and package characteristics; therefore, neither type of device is universally better or automatically interchangeable with the other.

How Should You Read a FET Symbol?

The first step in reading a FET symbol is to find the terminal (gate, source and drain) locations. Next check to see if you have either a junction gate or an insulated gate type, as well as whether you are looking at an N-channel type FET or a P-channel type FET, enhancement mode or depletion mode, and any shown body connection. These visual clues define which category of devices you are dealing with and how they will appear in schematic diagrams. However, the way that these visual clues are treated graphically will vary depending on which library or symbol standard you are following.

The channel line tends to be the next most helpful clue to determine which type of channel convention you have in a given library; solid or broken lines can denote depletion-mode or enhancement-mode FETs in a given library, while arrows may also be used differently in different FET subtypes. The official KiCad symbol libraries provide one practical reference.

No single sketch can show you all the JFETs, MOSFETs, body connections, or schematic conventions, so it is best to refer to the guide to reading transistor symbols for an overall approach. If you are looking for polarity-specific MOSFET arrows and terminal conventions, refer to the NMOS and PMOS symbol conventions.