HDI & Any-Layer PCB

What Are HDI PCBs and Any-Layer Structures?

HDI PCBs make use of laser microvias, blind or buried vias, smaller capture pads, and filled via-in-pad structures to free routing channels that PTH would occupy across the full stack.

Traditional HDI limits microvia reach according to planned buildup levels. Higher-order HDI is used when the required reach extends beyond the levels available in a simpler planned stack. Any-Layer HDI forms designed adjacent-layer transitions across the required stack, so its classification depends on the connected-layer map rather than finished layer count alone.

Interconnect Density Through HDI

With the increased interconnect density, it is possible to reduce PCB area, eliminate an additional routing layer, or keep reference planes continuous. For instance, with a properly executed layout, the designer may reduce an 8-layer layout to a 4-layer HDI design. This reduction is valid only when escape routing, copper distribution, impedance, current paths, and thermal reliability remain acceptable together.

How Does Any-Layer Change Interconnection?

The process of achieving routing flexibility incurs costs due to multiple lamination, laser drilling, metallization, copper filling, cap plating, and planarization. Registration errors, copper-distribution effects, dielectric variation, and surface topography are introduced in each cycle. As a result, transition count and the number of reachable layer pairs are the most important criteria for architecture selection, while layer count is less significant.

Which Microvia Structure Matches Each HDI Stackup?

Stacked vs. Staggered Microvias

Stacked microvias are the most compact of the three. They can be positioned directly on top of one another to create a single vertical path. Stacked microvias also provide the most direct means of connecting higher-order and Any-Layer routing levels; however, thermal expansion may stress the aligned plated interfaces. Target transfer, bottom capture, copper fill, cap thickness, and thermal expansion share the same vertical interface path.

Staggered microvias require a different configuration from stacked microvias because they are offset from one level to the next. The offset consumes additional routing space but reduces the length of the direct plated-interface chain. This reduction in direct alignment provides more latitude for distributing strain between the microvia connections. Selection follows escape density, available pad field, transition depth, and the required thermal-cycling evidence.

Via-in-Pad Under Fine-Pitch BGAs

Via-in-pad microvias are located within the component land; therefore, when the cavity is filled, capped, and planarized, the surrounding routing channels remain open. A component that uses a via-in-pad microvia must have a flat land. The land must be solderable without solder wicking into the cavity. Copper fill within the via helps retain solder on the land during assembly.

A representative 100 µm microvia may use an approximately 200 µm capture pad, while component-land geometry is defined separately by the BGA pattern. Capture pad, target pad, component land, and BGA pitch are not interchangeable dimensions. A final consideration when selecting microvias is the allowable void size and cap irregularities caused by poor processing, which may affect stacked-via reliability and solder volume under the component.

Any-Layer HDI PCB Stackup Design

Any-Layer HDI stack design begins by gathering the initial escape-row requirements, connected-layer reach, continuous reference planes, finished thickness, and maximum microvia-chain length.

How Many Sequential Lamination Cycles Are Required?

The SLC count is established by completing the placement of all signal, power, and ground layers before beginning the buildup process and then tracing all required point-to-point layer transitions. The minimum levels required to maintain return paths while minimizing routing distance to and from components will determine the thickness consumed by repeated buildups due to the additional dielectric and copper, regardless of whether the finished product target is an ultra-thin board. The general requirements for PCBs are provided in IPC-2221C; IPC-2226A is used for the design of HDI and microvia PCBs; IPC-6012F describes the qualification and performance requirements for rigid PCBs; IPC-A-600M provides a method for interpreting visual and microsection acceptance criteria in combination with the applicable procurement class. The PCB-specific drawing and purchase specification, along with the accompanying technical documents, define the values applicable to a specific design.

Fine-Pitch BGA Escape

The BGA pitch determines how much area is available for the component lands and how wide the escape channels will be, while the number of pins and rows helps determine how many transitions will be needed to route the pins from the component to the PCB. For instance, designs may use 0.8, 0.5, 0.4, 0.35, 0.3, or 0.25 mm pitch; even when two designs have the same pitch, the number of pins in each row and the row depth will determine whether different routing structures are required.

A 0.4 mm package may use a standard fine-pitch method because it has an open center, allowing the outer rows to escape directly. Conversely, a very dense 0.35 or 0.25 mm pattern may require via-in-pad routing to accommodate a greater number of rows. An open-center pinout can increase the available escape routes and reduce the required HDI order. Each review must include the following information: pitch, I/O count, number of rows, component-land diameter, microvia capture-pad size, routing layers used, and plane continuity.

HDI PCB Design Data

The engineering package should contain the following items: Gerber or ODB++, NC drill data, an IPC-356 netlist, the proposed stackup, copper weights, controlled-impedance targets, BGA land patterns, material requirements, finished thickness, surface finish, and reliability targets. The connected-layer map and via-fill information must be clearly defined before releasing the construction.

Low-Loss Any-Layer Stackups

The channel insertion-loss limit is determined by the data rate, edge rate, channel length, and Dk and Df at the relevant test frequency of an HDI stack. Copper profile and roughness also affect the same channel. The electrical parameters associated with Any-Layer structures must coexist with thin dielectric materials, repeated lamination, microvia formation, and compatible bonding materials.

SUGA supports MEGTRON 6/7/8, I-Speed, N7000-2HT laminate, N7000-3 prepreg, and RF substrates including RO4350B, RO4003C, RO4400-series bondply, PTFE, RCC, thin prepregs, and hybrid options. RO4350B and RO4003C have different flame-rating and processing requirements, so the respective bondply or prepreg must maintain resin flow and adhesion throughout the repeated lamination process. Material selection is determined by the channel-loss target, copper profile, laser response, dielectric availability, and complete stackup construction.

Microvia Reliability

The interface strength of each microvia is determined by its laser response, target-surface exposure, dielectric geometry, copper adhesion, plating uniformity, fill quality, cap planarity, laminate expansion, and total connected-chain length. Each failure mechanism must be connected to an inspection method that can detect it to validate microvia reliability.

Which Laminate Supports Laser Microvias?

Standard FR-4 can support cost-sensitive HDI when its thermal and electrical characteristics match the construction. High-Tg systems provide additional thermal margin, while low-loss materials address defined channel budgets. Thin prepregs and RCC provide the dielectric spans required by small laser apertures.

Laser response depends on glass style, resin condition, dielectric thickness, copper adhesion, and target-pad exposure. Resin must fill the surrounding topography without distorting the structure or causing thickness variation. Thin 1017, 1027, and 106 prepregs and a 14-layer Shengyi TG170 structure can be supported within the applicable stackup and lamination windows.

Failure Modes and Verification Methods

What Each Inspection Method Proves

AOI checks for opens, shorts, and pattern defects in the conductor image.

Finished-board electrical testing checks for continuity and isolation but does not reveal internal microvia geometry. X-ray checks for gross voids, buried alignment, and fill anomalies, while µCT provides three-dimensional localization when the feature and material contrast are sufficient.

Microsections directly measure target capture, copper distribution, bottom-interface condition, fill profile, and cap geometry at the sectioned location.

Resistance-monitored reflow, thermal cycling, or interconnect stress testing challenges latent interfaces by monitoring changes in electrical resistance under stress.

CAF and Thermal Fatigue Are Different Risks

CAF develops because the combination of voltage, moisture, conductor spacing, cleanliness, and the glass-resin interface supports a conductive path. CAF control begins with conductor spacing and material selection and continues through storage, lamination, cleaning, and insulation verification. CAF can result in leakage or unstable isolation.

Thermal fatigue occurs because the thermal expansion characteristics of copper and the dielectric differ.

The strain caused by thermal fatigue depends on bottom-interface geometry, fill condition, cap thickness, plating distribution, and the length of the stacked chain. CAF requires insulation-resistance evidence, while thermal fatigue requires resistance monitoring under thermal stress and physical interface analysis.

HDI PCB Cost

HDI PCB costs depend on both the finished layer count and the number of Sequential Lamination Cycles that a board has undergone.

For example, while two 14-layer boards may have the same finished layer count, they may have significantly different cost and yield exposure profiles due to differences in their structures. A 1+12+1 build has one buildup level per side, while a 2+10+2 build repeats laser drilling, plating, filling, planarization, and registration for each additional level.

The additional cost associated with Any-Layer HDI PCBs arises because adjacent-layer freedom is required across a greater percentage of the completed stack than in a more limited adjacent-layer application.

How to Reduce Cost Without Losing Routing Function

Limit the use of via-in-pad to areas of the PCB that do not allow dog-bone routing.

Use the shortest possible connected-layer paths through the board instead of carrying every layer-to-layer transition through the entire stack. Use standard dielectric spans and stocked material systems that are appropriate for meeting specified loss limits whenever they are available.

Use 50 µm apertures or 35/35 µm imaging only in areas that require these features, rather than imposing the smallest geometry across the entire panel.

Component rotation, pin swapping, power-pin grouping, layer reassignment, staggered transitions, and localized higher-order HDI can remove an unnecessary Any-Layer conversion.

Making changes to the layer-to-layer transition maps in the early stages of a project will lead to greater cost savings than trying to negotiate the same costs after release.