IC Board Design: From Datasheet to Verified PCB Inputs

What Does IC Board Design Mean?

IC design and PCB design are two different engineering disciplines, although both may sometimes be referred to as IC board design.

The difference between the two is the physical system being designed. IC design concerns the circuits and physical structures inside the silicon, while PCB design uses existing devices to create the schematic, footprint, PCB, and manufacturing artifacts. Synopsys describes IC design as circuit or logic design plus physical design; silicon-level tasks such as RTL, logic synthesis, place-and-route, GDSII, and foundry signoff belong to semiconductor design, while KiCad’s board workflow treats symbols, footprints, and PCB data as linked objects around an existing device.

PCB design inputs include the exact orderable part, package documentation, symbol pin mapping, footprint pads where the pins attach to the PCB, device requirements used as board constraints, and named verification used to check the released PCB against the intended requirements.

PCB layout should not begin before the electronic circuit schematic and device identity are sufficiently defined. Routing before the exact package, PCB land pattern, and pin-to-pad mapping are resolved only hides uncertainty that should have been resolved before designing the PCB.

Before layout, confirm four things: the exact orderable IC, the correct package and PCB land-pattern basis, a verified pin-to-pad mapping, and sourced electrical, thermal, mechanical, and interface constraints.

A direct-IC custom PCB requires verified device identification, library mapping, and device-specific constraints. A breakout board is different when a module already supplies the difficult package, support circuit, or connector access. An installed device with unknown markings must first be identified before it is treated as a design input. A bare PCB is an unpopulated circuit board, and a populated PCBA is the same circuit board with parts mounted on it. Thus, a purchase order or work order to produce a populated PCBA must refer back to the same controlled IC and package information. The assembly state is a manufacturing detail and does not provide evidence of device identity.

Which IC Are You Actually Designing Around?

Select an orderable component that satisfies your requirements for function, interfaces, supply conditions, environment, lifecycle needs, and current availability, and establish a controlled identity record. The functional selection determines whether the IC can support the electrical and interface requirements of your circuit. Package verification determines whether the physical characteristics of the device, including the footprint, thermal path, and assembly process, are compatible with the manufacturing capabilities of your circuit board. A component may pass functional checks but fail package checks.

This identity record should provide the manufacturer, complete MPN and suffix, package code, datasheet identity, package drawing, BOM status, and approved library revision. The Microchip package resource illustrates package type and code in its package outline drawings and shows why package documentation is an independent source of truth. Two devices may have the same pin count and a similar overall body outline but completely different exposed-pad configurations, thermal pad sizes, or terminal pitches, such as the TPS6216x family’s WSON and VSSOP options noted next.

The TPS6216x family is an example with defined parameters. The input voltage range is specified as 3 V to 17 V, the output current rating is up to 1 A, and the typical switching frequency is 2.25 MHz. The family is available in an 8-pin 2.00 mm x 2.00 mm WSON package and an 8-pin 3.00 mm x 3.00 mm VSSOP package (TPS6216x datasheet; TPS62160 product information). While both packages contain the same pin count, that does not mean they have the same land pattern, exposed-pad treatment, thermal path, or assembly review. If the package suffix is missing, the package code does not match the manufacturer’s records, the datasheet revision is unknown, or there is a difference between the BOM and CAD library, stop before performing the layout. Continuing with a likely but unverified footprint converts an identity issue into a physical failure that is much more difficult to diagnose.

How Do Package Pins Become Footprint Pads?

To have a valid footprint, the footprint pads must correspond to the actual pin mapping of the package, not just look similar. This step of verifying pin mappings is often skipped during the design process because the package drawing and CAD footprint may have been created at different times or from different revisions of the datasheet. Footprints created from older libraries may still have Pin 1 in the wrong corner relative to the current manufacturer drawing; however, the mismatch may not appear until the first hardware is inspected or assembled and the device is installed in the wrong orientation.

For exposed-pad packages such as the TPS6216x WSON, the cost of not performing this verification is more than cosmetic: if the exposed pad is unconnected or incorrectly sized, it can contribute to thermal limitations, increased noise sensitivity, or reduced EMI margin. These symptoms can appear during bring-up when the root cause is an incorrect or unnamed pad in the footprint.

Manufacturing capabilities must also be considered in addition to the datasheet parameters. For instance, the footprint lands may match the recommended land pattern, but the result may still be unsuitable if the fabricator’s solder-mask tolerances or the assembler’s stencil capabilities cannot reproduce the exposed-pad geometry accurately.

The direction in which the terminal order is drawn should match that shown in the drawing view. If a terminal view has been drawn in reverse sequence, it is possible that a mirrored terminal order could be used even if Pin 1 of a device has been identified as correct. An exposed pad carries several obligations including electrical, thermal, mechanical, and assembly responsibilities; therefore, an explicit net and implementation plan should be prepared for exposed pads rather than simply referring to them as “additional pads.” The cross-probing feature of KiCad is intended to illustrate relationships between symbols in the schematic and pads on the footprint; however, the ability to visualize the relationships does not indicate whether the actual content entered is correct (Schematic Editor 10.0). The package drawing serves as the definitive reference for the physical device, and the production footprint must reconcile not only the recommended land pattern, but also package application guidance, paste/mask treatment, and assembly process capability.

Changes in a package will alter the verification burden. The WSON option available with the TPS6216x example introduces exposed-pad, solder-paste, thermal-path, and land-pattern reviews that cannot be determined from the VSSOP name; the complexities that accompany package pitch, power dissipation, interface speed, thermal path, escape routing, and mechanical issues must all be considered when determining the degree of proof required for release. Pin count alone will not predict these complexities.

Turn Device Requirements into Board Constraints

Once an identification has been established, the source for each device requirement, the physical board artifact associated with each device requirement, the individual responsible for reviewing each device requirement, and the means of verifying fulfillment of each requirement will need to be recorded. Recommended Operating Conditions should be distinguished from Absolute Maximum Ratings. For example, the TPS6216x datasheet states that Absolute Maximum Ratings do not imply functional operation beyond the Recommended Operating Conditions; therefore, design and test limits must come from the applicable operating guidance, not the Absolute Maximum Ratings.

The exact datasheet and package drawing establish the device. The manufacturer’s recommendations for the land pattern and PCB layout provide the implementation details needed to manufacture the PCB for that device. For additional context on how the device, package, operating conditions, stack-up, and surrounding environment might relate to your specific application, review an EVM, Reference Design, or Application Note when those conditions match the intended use.

For example, TI provides design guidelines on Step-Down Converters. The guidance starts with the datasheet and EVM, and addresses the high-current loops around the device and their sensitive nodes (see “Five Steps to a Great PCB Layout for a Step-Down Converter“). For LMH121x, the guidance provides decoupling, exposed-pad, and frequency recommendations based on the device’s application in 12G-SDI. Each of these documents provides a unique category of evidence for each device and therefore cannot be interchanged between devices.

Be careful to document the provenance of all rules: where they came from (source), when they were last revised (revision), what units they were written in (units), which nets or pads they are associated with (affected nets/pads), who is responsible for reviewing them (reviewer), and what the method of verification was (verification method). A spacing rule of “3W” or “3H” cannot be used until you know the trace width or dielectric height on which it is based, which layer it is located on, and for which signal it is being used — thus, the same rule name may create a different physical spacing on a 2-layer board than on a 6-layer stack-up that has a buried reference plane. When using a fixed four-layer board stack, the risk is the same: without the operating frequency, dielectric constant, and routing context for which it was originally selected, that choice does not provide a valid design constraint. When interface behaviour makes dielectric properties relevant, they must be selected based on the actual stack-up configuration and operating frequency rather than by using a generic dielectric constant. As soon as you include a high-speed interface, these properties become inputs to placement and routing decisions.

Retain traceability for each design rule back to the specific net, pad, or component where the rule was applied throughout the layout process. The traceability is what allows a reviewer to verify compliance, rather than relying on memory of a paragraph someone had written. Once you have established traceability, you can convert these verified requirements into decisions for placement, routing, stack-up, thermal behaviour, EMC, and manufacturing factors.

How Do IC Requirements Change Placement and Routing?

A failure occurs when a requirement survives schematic review but is then translated into vague generalities, such as “keep it close” or “use a ground plane,” by the time the layout engineer receives the instruction. Such generalities have no specific references, such as a pin number, loop geometry, or numeric target, for the reviewer to verify compliance against. A layout engineer does not automatically have access to the pin number, loop geometry, or numeric target for a requirement that was created during the schematic review. The design intention is not simply “keep it close” or “use a ground plane”; it is to preserve the electrical, thermal, and mechanical behaviour required to support the specific IC’s performance.

An example is USB 2.0 High-Speed and its interface specifications for a signaling rate of 480 Mb/s and differential impedance of approximately 90 Ω. However, while those two specifications are fixed and defined by the USB 2.0 High-Speed interface specification, how the finished PCB will be designed to achieve a target impedance of 90 Ω can differ widely among different PCB designs. For example, the same target of 90 Ω could require a 6 mil trace on a board using a thin dielectric and could require a different trace width on a thicker stackup. The final trace width, spacing, and pair geometry depend on the dielectric properties, reference structure, board layer stackup, fabrication tolerances, connector topology, and device implementation guidance. Therefore, a routing rule copied without considering these factors will not be validated for that specific PCB.

The current-carrying copper must be determined based on the thickness of the copper conductor, the acceptable temperature rise, the construction of the PCB, and the guidance available at the time of the design rather than the application of a universal width rule. The relationship among current, conductor size, and temperature rise is discussed in IPC-2152 as it pertains to printed circuit boards.

For switching regulator ICs, the immediate issue is typically the geometry of the high-current loops and sensitive nodes; these should be validated by tracing the circuits to the original datasheet, EVM, and design or application guidance provided with the integrated circuits.

When Does Simulation Become Useful?

Simulation is most effective when the assumptions made for the simulation are explicit and understood. Prior to layout, circuit and topology analysis can verify assumed rail behavior, interface assumptions, or component selection. When there is no physical geometry to evaluate, the analysis is based entirely at the schematic level.

Post-layout risks such as impedance discontinuities, crosstalk, return-path breaks, IR drop, or thermal concentration can be evaluated through simulation of routing, stackup, and physical placement using the actual board geometry. However, not every electrical circuit requires every type of analysis. Simulations should be performed at a level commensurate with risk: timing margin and interface edge rate; package escape difficulty; thermal load; power density; regulatory exposure; and respin cost. Simulation should not be used in place of ERC, DRC, DFM, or bench testing.

Simulation is also only as good as the footprint and pin mapping on which it is based. Performing a post-layout thermal or impedance simulation before ensuring the accuracy of the identity and footprint checks defined in this section is wasteful because, if the footprint or exposed-pad mapping must later be updated, the associated simulation must be performed again.

What Must Be Proven Before Layout Begins?

Verified inputs have a source name and review responsibility assigned; therefore, verified inputs indicate where the data came from and who reviewed it, rather than confirming that the circuit has been built and functionally tested. Properly tracing a rail voltage from the schematic to the manufacturer’s datasheet does not eliminate the potential for the finished product to be defective. Identity review checks that the MPN, package drawing, symbol, footprint, and terminal map agree; ERC checks configured schematic rules, DRC checks board connectivity and geometry, DFM checks fabrication and assembly capability, and functional validation checks the real circuit. Passing one does not verify the others.

EDA software users should carefully consider their need for controlled library management, visible symbol-to-pad mapping, configurable design rules, required analyses and outputs, versioning, review or collaborative tools, and whether the tool can preserve the project’s design records and required fabrication, assembly, and test outputs.

AI-assisted EDA can automate portions of constraint handling, implementation, DFM, and multiphysics analysis, but an unknown package, incorrect pin map, or missing acceptance criterion still requires engineering review (Cadence Introduces AuraStack AI Super Agent).

Do not begin layout while a critical constraint has no source, a package or land-pattern basis remains unresolved, or an exception lacks documented engineering justification.

From Verified Inputs to PCB Layout

A design package is created with a complete set of controlled documents. The design package includes the exact part identification, approved symbol and footprint mapping, terminal assignments, land-pattern basis, reviewed schematic, sourced constraints, mechanical requirements, known exceptions, and verification plan, with compatible revisions and clear review responsibility.

A package designation can contain several variations of the same product; therefore, if the design package is not accurately identified, or if the designer or manufacturer is not able to confirm the package identity, the resulting board may not function as intended.

The designer should preserve the verified device requirements and confirm the integrity of the PCB routing before finalizing the design.

The designer should maintain a complete set of documentation illustrating both the initial design and all subsequent controlled changes throughout the design process. Fabrication and drill data should be checked against the released board database, and first assembled boards should undergo planned inspection, electrical checks, and functional validation; any mismatch should be corrected in the released design record rather than only in manufacturing notes.