XOR vs XNOR: Truth Tables Symbols and Uses

For two-input applications, the XOR circuit outputs 1 when the two inputs are different whereas the XNOR circuit outputs 1 when the two inputs are the same. Therefore, XNOR is the logical complement of XOR; this is detailed further in the function tables for the Nexperia 74HC86/74HCT86 and Texas Instruments CD4070B/CD4077B devices.

For devices that have more than two inputs, distinguish XOR reduction with a final inversion from cascading two-input XNOR gates. Also, distinguish these from Pairwise Word Comparison of data.

XOR vs. XNOR Truth Table

For binary inputs, Y_XNOR is the complementary signal to that of Y_XOR; Y_XNOR = NOT(Y_XOR).

XOR and XNOR Symbols and Boolean Expressions

The conventional ANSI representation uses the same shape as a regular OR gate, but has a second curved line on the input side for the XOR gate and an “inversion bubble” on the output side to denote the logical negation of the output for an XNOR gate, whereas Nexperia also publishes the IEC representation for the 74HC86 and 74HCT86 devices.

For binary inputs, the standard expressions for the XOR and XNOR gates are as follows:

• XOR: Y = A XOR B = A’B + AB’
• XNOR: Y = NOT(A XOR B) = AB + A’B’

XOR vs. XNOR: Key Differences and Uses

The Y signal produced by using control input (C) is a modified version of A’s signal which passes A if C=0, or if the condition of C=1 means A is inverted. The relationship between A and XNOR is the reverse of this polarity where A XNOR 0 gives the result as NOT A and A XNOR 1 passes A. For even parity, XORing all received data bits and the parity bit gives 0 when the received word has even parity and 1 when the received word has odd parity. An odd number of bit flips would cause the result to flip from 0 to 1. An even number of bit flips can go unnoticed.

How One Inversion Converts XOR and XNOR

The inversion of XOR produces XNOR, and the inversion of XNOR recovers XOR. For example: for an XOR gate with two inputs, XNOR(A,B) is equal to the inverted output of an XOR gate; thus, the output polarity changes while the input relationship remains the same.

The inversion of either input of a two-input XOR gate will also change the outcome of the two-input function: (NOT A) XOR B would also give A XNOR B.

Why Multi-Input XNOR Is Easy to Misread

After the first two inputs, the term “equal” does not define every XNOR-labeled circuit. XOR reduction, final inversion of that reduction, cascaded two-input XNOR gates, and pairwise equality should remain separate operations.

Nexperia 3-Input 74LVC1G386 outputs HIGH for 001, 010, 100, and 111 (74LVC1G386 3-input EXCLUSIVE-OR gate). The last row disproves an exactly-one interpretation.

Given three inputs, when A XNOR B is combined with C, the output is not the negation of A XOR B XOR C, it is equal to A XOR B XOR C. Each two-input XNOR added to the circuit creates an additional inversion, therefore as long as you keep a left-to-right association of XNOR gates, they will equal the combined result of XOR reduction for an odd number of inputs, but they will equal the inverse of XOR reduction for an even number of inputs. When A = B = C = D = 1 (HIGH), the left-to-right combination of 3 two-input XNORs produces a HIGH value, whereas doing an XOR reduction on a 4-input (A, B, C, D) produces a LOW value.

The modulo-2 operation used in CRCs and Hamming-code parity equations is performed with XORs. What the surrounding algorithm does determines which bits to combine and what to do with the results.

How XNOR Compares Multi-Bit Words

Multi-bit equality is when every corresponding bit pair of two words is equal. A parity reduction answers the question of whether the total number of HIGH inputs is of a particular parity.

For two n-bit words, the active-high equality function is:

EQ = (A0 XNOR B0) AND (A1 XNOR B1) AND … AND (An XNOR Bn)

For the same two n-bit words, you can obtain the same result by computing the XOR of every pair and performing a NOR on the mismatched results; if you find a mismatch, the output will be LOW.

Given A=1011 and B=1001, there is one mismatch in the pair (the third bits differ). The output of the pairwise XNOR gates, combined together with an AND gate, is 0, even though three of the four signals match (1,1,0,1). The TI SN74HC688 compares two 8-bit words. The EN signal has a defined output polarity in the data sheet (SN54HC688, SN74HC688 8-Bit Identity Comparators Data Sheet (Rev F)); however, the data sheet must be referenced to determine the levels of the EN signal and the function of the pins.

NAND Constructions for XOR and XNOR

An active-high XOR gate can be constructed with four two-input NAND gates (this configuration does not consider shared external inversions or constants). A 5th NAND will provide an inverted output for an active-high XNOR.

P = NAND (A,B)

Q = NAND (A,P)

R = NAND (B,P)

XOR = NAND (Q,R)

XNOR = NAND (XOR,XOR)

The four input rows yield XOR outputs of 0, 1, 1, 0. The self-tied 5th NAND gate will invert the XOR result to produce XNOR outputs of 1, 0, 0, 1.

Identical truth tables do not guarantee that two devices will behave similarly in terms of timing or analog behavior. To represent characteristics of devices which go beyond truth tables, the device-level or SPICE models must include propagation delay, input threshold, output characteristics, loading, and edge rates.

From Boolean Function to a Real Logic IC

TI SN74HCS266 contains four 2-input XNOR gates with open-drain outputs, Schmitt-trigger inputs, and a specified supply voltage range from 2 V to 6 V (refer to the data sheet of the SN74HCS266 for additional product information and support).

Many parameters must be checked when determining which XOR or XNOR IC to use:

• Logic family and supply voltage range
• VIH and VIL input voltage thresholds
• Output topology, pull-up requirements, and output drive capability
• Propagation delay, especially through cascaded stages
• Gate count, pinout, package, and unused input requirements

Open-drain outputs require a pull-up, and Schmitt-trigger inputs have different switching characteristics than standard CMOS inputs.

The term ‘DIP package‘ refers to how the body and the pin configurations of a package are organized, not the functioning of the XOR/XNOR logic. Two devices from the HC and HCT families may perform the same function and yet have different input voltage thresholds. In PCB design, the schematic symbol and footprint must match the selected device’s pinout.