What Is an HDI PCB Board? Vias, Layers and Routing

An HDI PCB combines fine conductor features (the traces/pads) with specific interconnections between layers to create a higher concentration of wiring within a given area (increased wiring density). HDI describes the method of arranging the conductors, pads, and vias throughout the structure, rather than the number of copper layers on the PCB, as in standard multilayer PCBs.

A plated through-hole is a hole that connects through the entire stack, using pads or clearances on intermediate layers it passes through. A short blind via or microvia stops at the layer needed for routing and preserves routing space below the layer to which it connects. This distinction highlights the advantages HDI and any-layer PCBs possess to support high densities of package escape routing without requiring every connection to pass through the entire PCB.

An HDI design is based upon an interconnect architecture and not simply a criterion of how many layers are involved. Selective vias retain routing channels that otherwise may be restricted by through-holes from top to bottom. Blind, buried, microvia, via-in-pad, stacked, and staggered describe different attributes. An HDI PCB architecture can be warranted by comparing the limitations of routing, thickness, or form factor with the added work of processing and validating the HDI design.

What Makes a PCB an HDI Board?

An HDI PCB incorporates multiple design features, including smaller land patterns, finer trace widths and spaces, thinner dielectric material between layers, more precise registration between layers, and shorter vias formed into the PCB between selected layers. The technologies of creating laser microvias, using sequential lamination to process PCBs, fine-line imaging of copper traces, and via filling are parts of the same technology set. One isolated blind via or a high layer count does not, by itself, establish an HDI architecture.

In contrast, a multilayer circuit board describes a printed circuit board that contains multiple patterned conductor layers. HDI describes the routing density and vertical connection management of a PCB within the structure. In addition, an ordinary multilayer circuit board may rely on many layers of circuit routing and mainly use through-holes, while an HDI-based PCB may provide for the escape of a very dense BGA through the use of one or more outer buildup layers.

Smaller land areas must match registration, dielectric thickness, plating, and inspection capabilities. Likewise, the usefulness of fine trace patterns depends on maintaining the finished copper geometry throughout production. An HDI PCB is designed and produced when conventional routing restrictions associated with packaging or enclosures no longer meet the required constraints.

How Do Selective Vias Free Routing Space?

A good example is when a component pad on the surface layer must connect to layer two. A plated through-hole reaches layer two but continues through every layer below it, where its barrel and clearances reduce available routing channels. A short blind transition will stop at layer two after making the required connection, so the deeper layers do not reserve clearance for that hole.

By using selective vias to create more routing space, the recovered area may allow another escape trace, preserve a plane region, or avoid adding a routing layer. However, it does not, by itself, make the PCB smaller or improve signal quality. These results depend upon how the released area, layer allocation, reference planes, placement, and electrical rules are used.

Blind, Buried, Microvia, and Via-in-Pad Explained

These terms are not interchangeable. Some describe which layers the connection reaches, others describe a small interconnect created in an HDI context, and others state where the via is positioned relative to a component pad.

A microvia may be blind when it connects an outer layer to a subsequent target layer. Once the laminated layer encases the microvia, it can become an “internal microvia” in the final product. A via-in-pad design can include various via configurations; however, for a pad that is intended for solderability, the via should not be left as an open hole; instead, it should be filled, planarized and copper plated over.

IPC-2226A defined HDI terminology and historical classifications for various types of HDI structures, but IPC now lists IPC-2226A as No Longer Maintained in the IPC revision table. Due to this, any current drawing relating to an HDI project should provide clear details concerning the actual via geometry, materials, acceptance criteria, and performance specification requirements rather than relying on a historical name alone.

How to Read 1+N+1 HDI Stackups

Generally, HDI stack labels utilize the outer numbers to indicate the sequential buildup layers on both sides of the stack, while the letter N or a parenthesized number in the middle references the core construction. An example of a 1+N+1 HDI stack has one buildup layer on each side of the core. A 2+N+2 stack has two buildup layers on each side of the core. The label does not identify all material types, via types, fill requirements or acceptance classes.

The example provided by TTM represents a 2-(4)-2 stack; it has two buildup layers on each side of the four-layer core stack. The identified name formats for HDI stacks can vary depending on the manufacturer, and therefore the approved drawing will be the primary source of authority for any particular HDI stack design. An indication of how processes are mutually dependent can be seen in how many levels of buildup a design has; each additional level may add lamination, via formation, metallization, filling, planarization, registration, and inspection work. For example, stacked microvias occur on the same axis through multiple pairs of layers, while staggered segments change their relative positions laterally; therefore, all of the interfaces will not be located within a single vertical column, but more routing space will be taken up than with stacked segments. Skip microvias skip an intermediate buildup layer and must meet the limitations of the applicable laser and aspect-ratio capabilities. Any-layer, also referred to as “every-layer” interconnection in some literature, allows suitable short connections through the layer stack, but one microvia does not extend through the completed board.

How Are HDI PCBs Manufactured?

The sequence may vary depending on specific materials and via architectures, but HDI PCB construction typically involves more steps than conventional multilayer circuit board construction.

1. Prepare the core or subcomposite by imaging the internal conductor layers, etching the internal conductor layers, laminating the central structure, and inspecting registration prior to the addition of buildup layers.
2. Add dielectric and copper to the stack by laminating the buildup dielectric materials and copper foils at controlled temperature and pressure conditions.
3. Image the conductor layer by applying photoresist, exposing the required design pattern, etching the copper, and cleaning the surface for further processing.
4. Create microvias using approved laser processes to make the microvia connections to the target lands without damaging the other layers or overshooting small pads during the drilling process.
5. Clean and prepare all microvia holes after drilling by removing any debris created while drilling and preparing the dielectric and copper surfaces for metallization.
6. Metallize, plate, and fill the holes as necessary by applying conductive material, building up the required copper, and filling the holes as appropriate for the stack or via-in-pad structures.
7. Planarize the surface for later lamination or component lands, then inspect for misalignment, fill quality, plating, and target-land connection.
8. Repeat the procedure for each subsequent buildup level until the last level is completed with the addition of solder mask, surface finish, electrical test, and any required reliability coupons or microsections.

Depending on the material and process being used (i.e., resin-coated copper, prepreg, additive processes, or alternative via technologies), the order of steps will vary. The one constant that will exist in the fabrication of each of these interconnect levels is a controlled interface involving material, registration, plating, and inspection.

Practical HDI Design Windows

Online design capability tables should be looked at as the starting point for a design and should not be viewed as a set of design rules that can be transferred to other designs. The suggested values listed below are useful for feasibility discussions at the early stages of the design process, and production limits must be determined by the specific fabricator that will build the PCB before layout release.

Specialized suppliers may have real abilities to create extreme-value products such as 20-50 um line and space or 25-50 um holes, but they are not to be presented as standard HDI rules. The production-ready design is based on demonstrated volume capabilities, not the smallest feature size produced during sample testing.

How Do Materials Affect HDI Performance?

The choice of materials affects the interconnect architecture because the dielectric must survive the processes of laser drilling, repeated lamination, plating preparation, assembly reflow, and service stress. The generic label of high-Tg FR-4 or low-loss laminate is not enough; rather, the chosen material must be linked to the electrical and thermal needs of the design as well as its manufacturing goals.

Laser drilling and glass structure. The amount of resin used, the type of reinforcement used, the thickness of the dielectric, and glass distribution influence whether the laser consistently reaches the target land. If a material has a tendency to leave behind bundles of glass or carbonised material in the hole, it may provide lower plating margins even if its previously quoted electrical properties indicate suitability.

Electrical behavior. Dk and the dielectric thickness determine the impedance geometry, whereas Df, copper roughness, and routing length affect insertion loss. Even though HDI can shorten a path and reduce stubs, it does not replace the need for stackup modelling or a continuous reference plane.

Thermal behavior. Tg, decomposition temperature, Z-axis expansion, resin flow, and the degree to which copper and dielectric adhere to one another all impact multiple lamination cycles as well as later reflow. High-reliability products must have their material sets evaluated according to their actual via stack and thermal history.

Process compatibility. The copper foil used, the chemistry of the fill, the types of surface treatments applied, and how planarization occurs must all be compatible with the selected dielectric. Impedance, registration, plating, and reliability can all be changed by making material changes after a stack is released.

Benefits, Costs, and Reliability Trade-Offs

HDI boards allow increased routing density through their design features because shorter vias occupy fewer unrelated layers and smaller lands provide more surface and inner-layer space. If the channels available on the HDI structure are efficiently implemented, it is possible to reduce the PCB’s board area, thickness, or number of layers. However, these improvements are not guaranteed results from every HDI board; they are dependent on efficient designs.

Improvements to electrical performance are also geometric in nature; for example, having shorter vias results in less via stub length and parasitic inductance than longer vias. The via-in-pad design may also provide for a shorter path from the land pad to the nearest reference or signal layer. However, if the return path has been disrupted, the reference planes are incorrectly assigned, or the routing design is unnecessarily densely packed, the benefits of a via-in-pad design may be greatly diminished.

The cost associated with constructing a PCB (HDI or otherwise) is determined by the process complexity and design efficiency of the PCB. In one published model of relative-board manufacturing costs, an 18-layer through-hole PCB, with approx. 100 pins per square inch, had been modeled as a 10-layer HDI structure with a 1+8+1 stack-up. The results of this model, a 28.1% relative cost reduction for this specific application, are not applicable to all HDI PCBs. Design decisions regarding panel utilization, minimum features, fill, material types, yield rates, testing, and volume will have an effect on the relative cost of a PCB.

Reliability is also dependent on factors related to the PCB’s design, including structure and materials, quality of the plating or fill, quality of registration, exposure to temperature during reflow, and acceptance testing. NASA and CALCE have documented failure modes related to microvia construction, including separation, cracking at corners or interfaces, void effects, and fatigue behavior. IPC has also reported latent failures that passed bare-board testing and appeared after reflow or exposure to system-level stress. A short via can be very reliable, provided it has been properly designed and manufactured. Nonetheless, the mere reference to short vias does not guarantee reliability. Bare-board electrical testing is used to confirm electrical continuity and isolation according to the supplied test data. In itself, it is not sufficient proof of resistance to assembly reflow or long-term thermal cycling. PCB electrical testing and verification should be used in conjunction with structure-appropriate coupons, inspection, and thermal validation if product risk warrants them.

Where Does HDI Solve a Real Constraint?

Consumer electronics, medical devices, automotive electronics, and high-pin-count digital products appear as different design challenges. However, they share a common problem—an escape, routing, or thickness constraint that cannot be satisfied by a conventional stack, rather than the product category itself.

Compact Consumer and Wearable Electronics

Consumer electronics such as cell phones, smart watches, earbuds, cameras, and other compact modules typically require high-I/O processors, memory, sensors, radios, and power circuits to be positioned around a battery and mechanical features. Thus, HDI is not necessarily related to the size of the product. Instead, it can result from a measured escape or layer-occupation issue caused by full-stack vias blocking inner routing, component lands consuming the available surface space, or enclosures restricting additional area and thickness. The use of microvias and via-in-pad creates opportunities to use local channels, but antenna clearance, battery spacing, flex connections, thermal spreading, and assembly access still create constraints on layout.

Medical Sensors and Implantable Devices

Numerous types of medical electronic devices are being developed; among these are wearable sensors, small-size monitors, hearing aids, catheter electronics, and implantable devices, which frequently require dense interconnections because sensing, processing, communication, and power functions share a tightly controlled volume. The benefits of HDI, which help route fine-pitch packages and shorten selected signal transitions, do not reduce the burden of validation due to miniaturization. Material traceability, cleanliness, ionic contamination, reflow history, test access, and thermal or mechanical reliability remain part of the design process. The stack and coupon plan should reflect the device risk rather than assuming that a smaller via is automatically more reliable.

Automotive Cameras, ADAS, and Radar Modules

Camera processors, radar front ends, communication modules, and domain controllers combine dense packages with high-speed interfaces, power conversion, connectors, and harsh temperature cycles. HDI can maintain routing under processors or memories while reducing stub lengths for specific signal transitions. However, HDI does not tackle the issues associated with heat, vibration, moisture, or electromagnetic compatibility by itself. Therefore, it is imperative to develop the reference-plane continuity, connector launch geometry, copper distribution, thermal path, and qualification conditions with consideration to the interconnect structure. For example, a design with only local BGA escape paths may utilize localized buildup, as opposed to requiring the entire PCB to have comparable levels of complexity.

Telecom, High-Pin-Count FPGA, and Avionics Systems

Despite the available board space, large FPGAs, network processors, optical modules, and avionics computers frequently exhaust traditional routing channels. These devices may require HDI when conventional routing channels cannot support thousands of package connections, reference-plane access, controlled-impedance breakout, or fixed board thickness. The advantages of using HDI to concentrate selective vias in the escape region while still permitting other regions to remain conventional are primarily due to electrical characteristics derived from the topology of the routing, rather than the HDI designation itself. Consider plane changes, return vias, power-distribution loops, loss budgets, and test coupons as determining factors for whether the shorter transitions can provide measurable performance improvements.

Does Your Design Actually Need HDI?

When it is not feasible to design a conventional stackup that meets an established package-escape, routing, thickness, or form-factor restriction with acceptable trade-offs, utilize HDI. There is no single BGA pitch that necessitates the use of HDI in all applications.

1. Look at the actual package used in the application. Examine the land pattern, populated ball map, breakout rows, power and ground assignments, and keepouts rather than just pitch.
2. Model usable routing channels. Apply realistic trace, space, via-land, clearance, and layer-allocation rules from the intended production process.
3. Protect system constraints. Check reference planes, return paths, power distribution, assembly and test access, board thickness, thermal paths, and mechanical boundaries.
4. Try conventional alternatives. Assess package or pinout changes, placement changes, additional conventional layers, and localized redesigns before proceeding with sequential buildup levels.
5. Escalate with evidence. If the design constraint persists, obtain a confirmed stack, via structure, material set, process limits, and validation plan before layout release.

For example, an ultra-dense processor may be unable to provide escape routing for internal ball rows under the approved rules; this type may require selective interconnects, whereas another device with the same nominal BGA pitch may be able to utilize a conventional routing process based on package pin layout or board placement.