PCB Fabrication Inspection & Bare-Board Testing Capabilities

Which PCB Testing Method Fits Each Diagnostic Need?

Within SUGA's manufacturing capabilities, the selection of methods for PCB testing begins with determining the end result to be demonstrated, the physical or logical access available, and the required diagnostic depth. Continuity cannot verify impedance or function, AOI cannot confirm hidden electrical behavior, and functional pass/fail results do not always help identify defective nodes.

Bare-Board Electrical Tests

Bare PCBs should be tested based on the approved revision of the Gerber or ODB++ data files, along with their drill and netlist files. When a board shows an open circuit, it could result from an open on the board, unstable probe contact, or a Gerber/netlist revision mismatch. Therefore, repeated contact checks and other evidence of failure must be documented separately before making a final determination of where the fault originated. TDR also relies on the launch, coupon, or target trace being representative of the board's design. Passing continuity does not ensure controlled impedance, full current-handling capability, or the proper function of an assembled PCB. SUGA maintains records of the board or lot identity, the applied test limits, the locations of any failures found on the board, the test setups, the waveforms produced during testing, the PCB profiles, and the values measured during high-speed diagnosis.

ICT, Flying Probe, and Boundary-Scan Access

When a PCB has a test point, coverage can only be established if probe size, approach angle, component-height clearance, board support, coating access, and reference connections are usable. During value, polarity, presence, short, open, and programmed-operation checks, the contact between the test probe and the test point is verified for accuracy, along with the test-fixture wiring and connections, guarded measurement conditions, the current revision of the test program, and the approved test limits. Product failures can be simulated by worn-out pins, contaminated pads, PCB flex during testing, relay resistance, or the wrong version of the test program. Boundary-scan testing or functional interfaces therefore provide logical access where physical probing is restricted; however, these tests do not replace analog, power, or mechanical testing.

Powered Functional Verification

Protected power-up testing requires the current limits of the power rails to be defined in advance, the power-rail sequence to be specified before powering up the PCB, the safe I/O states to be clarified, and the firmware and configuration revision to be known. Defective devices, residual shorts, incorrect component orientation, operating state, fixture load, and firmware can cause abnormal current. Supply conditions and rail evidence must be collected before broader operational stimulus is applied. During functional testing, all necessary data must also be logged for communications, sensor channels, alarms, outputs, load switching, and system states.

Successful interface connectivity should not be considered proof of current margin under load, boundary conditions, or continuous operation over an extended period.

Cleanliness and Leakage Analysis

To determine cleanliness levels and leakage susceptibility associated with a given PCB, ROSE testing and ion chromatography may be performed. Although ROSE provides information regarding bulk cleanliness and process trends, it does not identify the location of PCB contamination or prove circuit reliability. Ion chromatography is used to determine the presence of extractable ion species in PCB contaminants. The SIR test is used with humidity-bias testing and subsequent PCB circuit-node measurements to determine whether leakage from PCB contaminants occurs under the specified voltage, humidity, and time conditions. Local residue analysis may be required if the result of a ROSE test conflicts with stability data from high-impedance circuit nodes.

Thermal and Powered Screening

Thermal cycling screening identifies failure modes related to thermal-profile fatigue, while powered burn-in testing identifies failure modes related to prolonged powered operation. Therefore, a PCB that passes one mode of testing could still carry the risk that the other testing mode was designed to detect.

Each unit is identified and recorded according to its profile or duration, monitored parameters, acceptance limits, failures, and post-screen results. Any recorded failures or results marked as “pass” are directly linked to the same monitored unit so that an intermittent or temporary change is not missed by replacing the sample or measurement setup.

How Does the PCB Testing Process Move from Design to Re-Test?

Design Data Alignment

SUGA will align Gerber or ODB++, drill, netlist, BOM, placement, schematic, firmware, test specifications, load definitions, and the expected-results format to the same revision before starting fixture or program work. When there is a conflict between the drawing and specification, drawing and contract, drawing and approved exception, or specification and approved exception, SUGA will resolve the conflict by determining the controlling document and precedence and will inform the customer of the resolution before programming limits. When the hardware, BOM, firmware, limits, or acceptance criteria change, those changes will trigger a re-evaluation of the affected method and results.

Bare-Board Checks

The quality of the bare boards is judged based on workmanship, dimensions, material condition, outline, holes, and specified geometries. Network continuity and isolation are verified against approved source data, while TDR analysis provides evidence of the controlled-impedance properties of the manufactured boards. Contact-related repeat inspections are separated from repeatable board failures before disposition to prevent avoidable bare-board defects from consuming components and assembly work.

Assembly Process Inspection

Any issues related to print excursions return to stencil and print controls, indications involving under-package joints proceed to X-Ray and electrical correlation, and first-article results confirm that the intended materials, programs, criteria, and inspection sequence are correct. Visible failures and hidden structural failures are resolved before broader functional or electrical testing so that failures occurring at a later stage of the testing process can be diagnosed against a valid assembly condition. A repair, material change, program change, or process adjustment causes the affected inspection process to be repeated before the PCB moves forward.

Re-Test After Repair

A protected power-up check identifies the rail sequence, the current being drawn, and the immediate risk before broader stimulus is applied to the network. ICT or flying probe rechecks the accessible networks that may have been disturbed during the repair, and functional testing employs the appropriate firmware, interfaces, signals, loads, and expected responses. The re-test plan follows the failure mechanism; a replacement component may need to be evaluated for polarity, solder, node condition, power-up, calibration, and function rather than repeating only the test that originally failed.

Following diagnosis of an FCT failure, the root cause must be established among assembly, component, design-data, firmware, fixture, test-program, and limit errors. The repair process requires containment and authorized disposition to be documented in the NCR, and every inspection or test affected by the repair must be repeated. Final approval may only be given after linking the original failure, before-and-after results, repair, re-test, and applicable lot-level feedback to the same hardware identity.

How Do PCB Testing Capabilities Change from Prototype to Volume?

PCB Test Point Access

SUGA compares all Gerber or ODB++ files, drill files, netlists, BOMs, placement files, schematics, firmware, and test requirements and maps all signal nodes, grounds, references, connectors, and supported digital paths. This comparison shows reachability for flying probe, ICT, boundary scan, bench measurement, and functional interfaces, while showing all networks that can only be tested indirectly.

Test points should have the proper probe size, approach angle, component clearance, keep-out from adjacent parts, coating access, connector configuration, and mechanical support. DFT identifies access limitations before fixture release and separates physical probe access from logical access through firmware, boundary scan, or product interfaces. Logical access extends digital coverage; however, logical access alone is not sufficient to validate analog values, insulation, solder geometry, or mechanical integrity.

PCB Test Fixture Integrity

PCB test fixtures are maintained through control of the mechanical interface, wiring, revisions, maintenance requirements, spares, calibration linkage, measurement sequence, diagnostics, limit sets, and software versions. Matching programs to products ensures that repeatable results are produced on the correct hardware and firmware. Fixture self-checks separate worn contacts, relays, cables, and reference failures from DUT failures.

Golden boards and other references are uniquely identified, with the approval basis identified for each fixture type, stored under controlled conditions, periodically checked for damage and aging, and replaced as necessary. If any fixture, program, limit, reference, product, or process is changed, all measurements and tests affected by that change must be repeated.

Prototype-to-Volume Strategy

The prototype and engineering debug phases emphasize flexible access, rapid program revisions, detailed failure localization, flying-probe testing, bench measurement, protected power-up, targeted FCT testing, and risk-based X-Ray. During NPI and first-article testing, coverage, false-call management, fixture mechanical integrity, operating limits, unique reference identification, and result formats are stabilized before transfer to high-volume production.

The high-volume production phase emphasizes repeatability, cycle control, trend visibility, false-call management, unit or lot traceability, and repair history. Dedicated inspection and fixture-based testing are used where justified by access, volume, cycle requirements, and defect history. Trend excursions, fixture wear, escapes, or product changes trigger containment and focused validation.

PCB Testing Applications by Product Risk

Patient Monitor Mainboard

The testing of a patient monitor mainboard combines SPI and AOI for paste, polarity, placement, and visible joints, with risk-based X-Ray for hidden packages. The rails and sensor networks of the patient monitor are tested with ICT or flying probe. A functional and calibration test is performed by applying a traceable sensor stimulus to measure accuracy, calibration, alarms, display, and communication. The primary risk is confusing DUT error with stimulus-source error, channel crosstalk, or an incorrect calibration state. Network measurement, stimulus verification, alarm-threshold and response tests, and repeated calibration help isolate a wrong value or connection and confirm sensor-channel accuracy.

Automotive Control Unit

Placement, polarity, and under-package joint inspection is performed on an automotive control unit. Electrical and functional tests of the automotive control unit are performed through accessible networks to verify CAN or LIN communication, wake and sleep current, power sequence, loads, protection outputs, and diagnostic states. A sleep-current measurement requires the proper stabilization time, network state, and termination; otherwise, an intermittent connector or supply dip could appear as a communication-protocol or firmware fault. To isolate solder, power, interface, and firmware faults and confirm stable communication under sustained bus load, connector inspections, X-Ray, node measurements, current logs, and repeated bus testing are conducted.

Motor Drive Control Board

Visual and optical inspections are performed to verify power-device placement and polarity on a motor drive control board. Hidden power joints are verified by X-Ray. Isolation or Hi-Pot testing is conducted to verify the insulation structure, while protected power-up and functional tests are performed to verify gate drive, current feedback, phase output, temperature input, current limiting, and shutdown under controlled load. High-side gate measurements, dead time, probe reference, and load symmetry must be controlled because the measurement setup can imitate shoot-through risk or phase imbalance. Gate signals, sense measurements, solder evidence, and repeated load testing localize phase-current mismatches and confirm motor-output behavior.

Battery Management Control Board

AOI is used to control the placement and polarity of components. Connections to cell-sense and protection networks on the battery management board can be tested by flying probe or ICT probes. The isolation test checks that the voltage structure matches the specified requirements. FCT includes using a precision cell simulator and contactor or load simulation to determine channel error, cell balancing, communication with the microcontroller, contactor logic, and overcurrent and overtemperature protection limits. Simulator uncertainty, open-wire behavior, contact resistance, and heating of balancing resistors can result in a channel shift without a permanent component failure. The use of reference stimulus, resistor-network measurements, solder inspection, thermal inspection when applicable, and repeated protection tests will then isolate potential channel drift and verify that the measurement is accurate.

Agricultural Sensor Gateway

The inspection of the ASG considers connector condition, polarity, coating boundaries, and solder condition, using ROSE testing as a screening tool to detect residue and contamination. IC, SIR testing with humidity bias, and local-node measurement can be used to confirm contamination suspected from the ROSE result. Coating can conceal residue and prevent access to contamination that is present near a high-impedance node. Leakage from this node can occur through the combined effects of humidity and electrical bias. Electrical access and FCT test sensor inputs, wireless links, field protocols, indicators, and firmware. Connector evidence, input stimulus, protocol logs, high-impedance measurements, and analytical testing will isolate contact, contamination, power-supply, and firmware causes under the specified humidity or bias condition.

AI Accelerator Board

The use of SPI and AOI allows control of dense component placement on the AI accelerator board, while X-Ray or CT is used to inspect the BGA structures. Boundary scan verifies supported interconnects, TDR locates impedance discontinuities, and protected power-up determines the appropriate power-rail sequence and current. A connected link does not necessarily indicate eye margin or stability at temperature or under sustained-load conditions. VRM performance, the BGA interface connection, channel loss, reference-clock input, and firmware training can also cause similar symptoms. BERT or PRBS loopback, eye and interface diagnostics, link-training logs, firmware checks, and sustained-load tests identify causes associated with channel transitions, BGA connections, power, and firmware, and confirm that powered links are stable.

Avionics Control Module

The avionics control module combines workmanship information and evidence of under-package joint conditions with network-check results, protected power-up, interface stimulus, I/O loads, monitoring information, and the temperature, vibration, or powered profile required for the program. Determining the correct mapping of connector pins, the deterministic timing of the I/O ports, and intermittent functioning of the module during profile transitions require control. An avionics control module that passes the room-temperature prototype test may still fail during the required temperature profile. The following evidence helps isolate power-supply, interconnect, component, or firmware causes during the required temperature profile or acceptance class: supply logs, connector and solder inspections, interface records, and repeated profile tests.

Rugged Communication Board

Inspection of a rugged communication board includes inspection of connectors, physically large components, solder-joint condition, coating boundaries, and under-package joints. Electrical and functional testing consists of measuring the power rails, identifying the interfaces, radio or data links, I/O controls, and loads, and conducting functional testing of firmware behavior under the specified operating conditions. Environmental screening involves thermal and vibration testing to verify that all electrical and functional components remain operational and within specified limits. A dropped link may be attributed to many causes, including connector fretting, RF-path loss, digital baseband faults, and unstable supply. Changes in and confirmation of link performance after exposure are documented through before-and-after images, node measurements, link logs, path-specific checks, and repeated tests.