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HDI & Any-Layer PCB
HDI PCB Fabrication in China for Microvias
A High Density Interconnect (HDI) PCB quote for OEM engineering and procurement teams is usually based on a build-up structure, microvia and via-in-pad data, quote fields, and board-level data documenting what the fabricator is being asked to manufacture. To forecast pricing or release a board, an HDI PCB request is most useful when it clearly separates standard multilayer, true HDI, and any-layer requirements.
HDI Build-Up Structures and Fabrication Pricing
The HDI PCB cost basis is determined by the board’s build-up structure and its manufacturing path. Pricing for standard multilayer boards that only use through vias will differ from HDI boards, such as 1+N+1, 2+N+2, 3+N+3, any-layer, or via-in-pad HDI. The basis for HDI PCB price comparison is derived from the build-up structure indicated in the stackup and drawing.
Standard Multilayer vs HDI Interconnect Structure
The interconnect structure depicted in the stackup and drawing establishes the fabrication type for a board. Transitioning from standard multilayer to HDI typically increases connection density, so pricing reflects the added process work. Traditional multilayer pricing considers layer count, through-hole structure, registration, etching, and plating tolerances. HDI boards typically add laser-drilled microvias, build-up layers, sequential lamination, stacked connections, or filled and capped via-in-pad features.
HDI Build-Up Structures and Fabrication Pricing
| HDI Structure | Density Driver | Stackup Data to Release | HDI Structure on Drawing | Fabrication Constraint | Pricing Effect |
|---|---|---|---|---|---|
| Standard multilayer; no HDI structure | Moderate routing density | Layer count from stackup drawing | Through-via structure | Registration and etch tolerance | Priced as standard multilayer |
| 1+N+1 HDI | Fine-pitch breakout on outer layers | One build-up layer per side | Blind microvia | Laser drill alignment | Moves quote from standard multilayer to HDI process |
| 2+N+2 HDI | Higher routing density under ball grid array (BGA) packages | Two build-up layers per side | Blind and buried via stack | Sequential lamination constraint | Sequential lamination count changes pricing basis |
| 3+N+3 HDI | Dense signal escape and compact layout | Three build-up layers per side | Multiple microvia layers | Registration and plating stack control | Fabrication review before pricing |
| Any-layer / every-layer interconnect (ELIC) HDI | Layer-to-layer microvia connection | Every-layer interconnect map | Microvia path by layer-pair | Stacked microvia reliability concern | HDI process capability confirmation needed |
| Via-in-pad HDI | BGA pad escape and routing compression | Pad, via, and filling data | Filled and capped via | Filling and capping process constraint | Via filling and capping add separate quote lines |
The pricing basis changes the most due to lamination sequence control, stacked microvia judgment, and filling and capping work associated with 2+N+2 or 3+N+3 build-ups, any-layer structures, or via-in-pad designs compared with standard through-via multilayer.
Via-in-Pad as a Pricing Item
Via-in-pad costs are not always separate items on quotes; they become adders when the quote includes pad filling, cap plating, and finished-pad acceptance. A component pad with an open via, a filled via, or a filled-and-capped via will require different amounts of fabrication work.
A common RFQ omission is not the pad position but the missing fill and cap callout on the drawing. While the drawing may only show a via below the pad, one fabricator may quote based solely on the position information, while another includes fill, cap, and surface acceptance work.
In order to provide an accurate quote, include the fill type, cap condition, finished-pad acceptance for the pad, and whether the callout for fill and cap applies to each pad or only to selected BGA escape locations.
Any-Layer HDI Needs a Layer-Pair Interconnect Map
An any-layer HDI PCB is planned using a map that describes how each layer connects to the next. In a standard HDI build, microvias may only connect a specific build-up layer. In an any-layer construction, microvia connections may span multiple layer-pairs, so the entire interconnect plan becomes part of the manufacturability check.
ELIC Structures and Every-Layer Connections
ELIC structures use every-layer interconnects. The planned microvia connections include board-level interconnections rather than just those at the outer build-up layers. The key release item on every ELIC structure is the layer-pair map, which shows the layer-pair connection, microvia starting and stopping points, and whether the design uses stacked or staggered structures.
A dense multilayer board may still contain conventional buried and through vias. Manufacturing an any-layer HDI board typically requires greater precision in microvia hole size, registration control, plating, and microvia stacking because the interconnect structure is repeated across more of the stack than in a conventional multilayer construction. The layer-pair map separates limited build-up work from an every-layer interconnect stack. That difference affects lamination sequence, stacked-via planning, via-plating review, and the documentation required before assembly.
Stacked Microvia Risk in Any-Layer HDI
Stacked microvia failure risk is important in any-layer HDI design. When microvias are vertically aligned, the interconnection structure must be registered correctly, plated consistently, and connected continuously through the stack to support a successful build. Via locations shown on the drawing do not guarantee that the finished board meets the specified acceptance criteria. Gerber data alone can omit this assessment. The way the microvia structure will be built before assembly must be defined by the stackup, start and stop layers for each microvia, via stack information, and coupon or microsection callouts.
The detailed specifications in the any-layer request include three elements: the layer-pair interconnect map, the stacked or staggered microvia configuration, and the anticipated pre-assembly board records. This specification prevents the HDI board design from being priced like a generic multilayer quotation.
Microvia Data for Drill, Fill, and Registration Risk
HDI laser microvia PCB capabilities depend on more than the drill symbol in the file. The drill package includes the microvia specifications for each microvia callout. Laser microvias, blind vias, buried vias, stacked microvias, staggered microvias, and via-in-pad configurations create questions about microvia hole depth, layer-pair registration, plating, filling, capping, or acceptance of the bare-board structure defined by the drawing or Purchase Order (PO).
Laser Microvia Start and Stop Layers
Laser microvia drilling definitions include the start and stop layers, target pad information, finished microvia size, and intended layer-pair interconnections. These details define drilling depth and registration before the build can be treated as a repeatable HDI build. An L1-to-L2 microvia and a stacked microvia chain across multiple build-up layers create different drilling and plating verification requirements.
Separate blind and buried vias in the drill package. A blind via reaches the board surface, while a buried via remains within the stack. Mixing these via types can obscure the lamination sequence or hide the internal via architecture needed to complete the final board build-up.
Microvia and Drill Risks in HDI PCB Fabrication
| Via and Drill Feature | HDI Routing Function | Drill File Data | Fabrication Drawing Field | Failure Mode or Process Limit | Bare-Board Check |
|---|---|---|---|---|---|
| Laser microvia | Fine-pitch breakout on build-up layers | Laser drill file with start and stop layer-pair | Microvia size, target pad, and layer-pair | Laser depth control, registration, and plating consistency | Drawing-defined HDI requirement |
| Blind via | Surface-to-inner layer connection | Blind via drill data by layer-pair | Blind via callout and finished hole requirement | Misregistration or incomplete connection to target layer | Bare-board acceptability |
| Buried via | Internal layer-to-layer connection | Buried via drill file before final lamination | Buried via layer-pair and plated hole requirement | Lamination sequence error or internal plating defect | Netlist-based electrical test when supplied |
| Through via | Full stack connection | Mechanical drill file | Finished hole size and plating requirement | Hole wall plating or aspect ratio constraint | Hole and plating check stated on drawing |
| Stacked microvia | Vertical high-density interconnect path | Microvia stack data by layer-pair | Stacked via structure and permitted stack height | Registration buildup and plating stress across the stack | Microsection or coupon check when required by drawing or PO |
| Staggered microvia | Offset high-density interconnect path | Microvia locations by layer-pair | Staggered via pattern and separation | Pad capture and registration shift | Microsection or visual acceptability check when required by drawing or PO |
| Via-in-pad | BGA pad escape and routing compression | Pad and via location data | Via-in-pad callout with filling requirement | Solder wicking risk or unfinished pad surface | Filled-pad condition checked to drawing |
| Filled and capped via | Finished pad surface before assembly | Via fill and cap specification | Fill type, cap condition, and acceptance requirement | Void in fill, cap depression, or uneven pad finish | Visual or microsection acceptability |
The highest-risk items are laser microvia, stacked microvia, and via-in-pad when evaluating risk in HDI PCB fabrication. Laser microvia risk centers on drill and plating control, while stacked microvias add registration risk through the stack. Via-in-pad also creates additional risk due to fill and cap conditions of the assembly-facing pad surface.
Via-in-Pad Fill and Cap Conditions
When a drawing provides RFQ data for via-in-pad routing within dense packages, it turns from a routing feature to a pad-finish item; if there are no references indicating whether the pad is open, filled, capped, or finished, the RFQ has omitted this information. Separate via locations from their fill and cap conditions.
Stacked vs Staggered Microvia Risk
Stacked and staggered microvias serve different purposes in solving high-density requirements. Stacked structures provide a vertical interconnect path; staggered structures offset the interconnect path while still requiring pad capture and layer-pair spacing verification.
To define the via structure as a board feature, instead of identifying it with a generic HDI label, drill files, layer-pair definition, and via fill or cap specification should be included with the fabrication drawing.
HDI Quote Fields for China PCB Fabrication
Layer count alone does not provide enough information to bind an HDI quote together. Changes in lamination sequence, material selection, impedance control, copper build, surface finish, and acceptance class indicated on the fabrication drawing or PO will all provide grounds for price fluctuations. Compare fabricators only after they receive the same build inputs.
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HDI PCB Stackup and Material Data for Quote Comparison
The first reference point when pricing an HDI job is the HDI PCB stackup, as it establishes the layer build, dielectric structure, and lamination path. For HDI projects, the stackup represents a lot more than just a layer count; a detailed description of a released stackup is required to differentiate between multilayer pricing, sequential lamination, and microvia pricing.
If the material line is left open, one quote may include a substitute, while the other references the laminate listed in the quote, which will make it impossible to make a pricing comparison.
HDI PCB Stackup, Material, and Impedance Data for Quote Comparison
| HDI Quote Field | Fabrication Decision | Pricing Assumption Created | Quote Input or Evidence |
|---|---|---|---|
| Released HDI stackup | Layer count, dielectric build, lamination path | Quote based on unverified layer build | Released stackup with layer build and revision |
| Material / laminate specification | Laminate family, glass transition temperature (Tg) / thermal decomposition temperature (Td) class, resin system | Material substitution risk | Laminate spec or listed substitute entry |
| Dielectric thickness | Impedance, lamination, and copper balance | Impedance and registration assumptions | Dielectric thickness table for impedance and lamination check |
| Finished copper specification | Etch allowance and plating build | Trace width and plating mismatch | Finished copper table tied to etch and plating build |
| Controlled impedance specification | Coupon, trace geometry, and test need | No impedance report basis | Impedance table with coupon / report basis |
| Surface finish line | electroless nickel immersion gold (ENIG), organic solderability preservative (OSP), immersion silver (Imm Ag), immersion tin (Imm Sn), or other finish | Solderability and shelf-life uncertainty | Surface finish in PO or fabrication drawing |
| Class / acceptance class | Bare-board acceptability level | Class drift between quote and build | Acceptance class traceable to drawing, PO, or acceptance criteria |
The most sensitive inputs are the released stackup, dielectric and material definitions, controlled impedance target, and defined acceptance class or IPC performance class stated on the drawing, PO, or acceptance criteria. These inputs do more than change the quote documents; they define what the fabricator needs to procure, document, and price.
Impedance, Copper, Finish, and Acceptance Class
Controlled impedance is identified in the quote prior to comparing copper data; it establishes trace geometry, dielectric selection, coupon planning, and the basis of the impedance report. If an impedance table is not supplied, the coupon and report scope remain ambiguous.
The finished copper type impacts etching allowance and plating build; the surface finish line will impact solderability expectations and the potential shelf life of the finished board. These decisions are made during fabrication of the HDI boards — they are not cosmetic.
Acceptance language must also be traceable to either the drawing, PO, or acceptance criteria; if an acceptance class or IPC performance class is listed on the quote, that acceptance classification can vary once a build is made if it does not have a fixed source from which it was quoted. Confirm these inputs before accepting the price difference as indicating the same build requirement.
Bare-Board Records Before HDI Boards Enter Assembly
Bare-board records provide evidence for board-level release checks before HDI boards enter assembly. Each record is designed to respond to one board-level question only. Separate assembly documents, test conditions, or project standards files are required to perform functional testing, inspect solder joints, or confirm product-level compliance with target-market standards.
Electrical and Impedance Records
Bare-board electrical test records are generally related to the netlist or the test requirement as indicated by the drawings or PO. For dense HDI routing, particularly when critical nets are used, this testing supports continuity screening across the board. As there are no components, firmware, loads, or final assembly behavior during this testing phase, the actual functional behavior of a printed circuit board assembly (PCBA) does not fall within the scope of these records.
Impedance records serve a different purpose. By taking all measured impedance groups and comparing them against each controlled impedance net’s target and tolerances, a board-level signal-integrity check can be supported. However, final RF and product-level performance requires assembled-product validation, assembly inspection, or functional PCBA testing.
Before requesting release records, give the fabricator a list of the drawing class, netlist, impedance table, coupon callout, or declaration request to document.
Bare-Board Records Before HDI Boards Enter Assembly
| Record Type | When It Is Needed | Drawing, Netlist, or Record Field | Board Decision Supported | Does Not Prove | Request Condition |
|---|---|---|---|---|---|
| Bare-board visual acceptability | Drawing class or PO acceptance clause | Class, surface condition, hole condition | Visible board condition accepted or flagged | Assembly solder quality | Visible finish or hole concerns on HDI board |
| Bare-board electrical test | Netlist or test need from drawing / PO | IPC-D-356 netlist format when supplied | Open / short screening result available | PCBA functional behavior | Dense HDI routing or critical nets |
| Impedance test documentation | Impedance table and released stackup | Target impedance and tolerance | Measured impedance group compared with target | RF or system-level performance | Controlled impedance nets in released data |
| Microsection or coupon record | Coupon required by drawing or PO | Coupon location and via structure | Plating and via structure documented | Long-term field reliability guarantee | Stacked microvia or plating concern |
| Material and compliance declaration | Material or order-level declaration need | Laminate, finish, RoHS and REACH declaration | Shipment declaration package supported | Full product compliance alone | Regulated product or declaration request |
Record Type Must Match the Board Decision
Each record responds to a board-level question. Records for visual acceptability, E-test output, impedance records, coupon results, and material declarations all support different checks. If each check stays connected to its true accept-or-reject point, the release records are easier to compare before assembly.
Microsection, Coupon, and Declaration Limits
Microsection or coupon reports are useful when the go/no-go point is plated structure, via stack condition, or a coupon callout found in either the drawing or the PO. Microsection and coupon reports document the location and structure of the coupon that was specified in the request. Long-term field reliability still depends on the design application, assembly conditions, environmental factors, and product validation.
Material and compliance declarations must be written carefully. A RoHS or REACH declaration at either the material or order level can be used to support the shipment records for the specified order. If full product compliance is being requested, additional component data, assembly material records, target-market requirements, and compliance files may be needed.
For HDI PCBs, the most appropriate release point prior to assembly is a release record produced to address the bare-board checks requested for release. Solder-joint inspection, electrical tests under load, and product compliance evidence need PCBA inspection data, test scope, or compliance files.
When HDI Density Is Not the Main Fabrication Driver
When HDI density is not the main driver, the request should be prioritized by the manufacturing factor that controls the build. Density and microvia configurations keep the work within HDI fabrication. RF material behavior, flex construction, current-carrying needs, embedded components, or PCBA evidence can shift the quote toward a different fabrication or assembly requirement.
Standard Multilayer PCB vs HDI Build Requirements
Standard multilayer PCBs can still be dense, high layer count, or impedance controlled, so HDI designs begin to differentiate themselves when they contain one or more of the following characteristics: build-up layers, blind microvias, staggered or stacked microvias, via-in-pad, or any-layer interconnect features that alter the fabrication method.
For example, if there is only a conventional through via on a PCB when it is sent out for quote, it will be considered a standard multilayer PCB build. If a PCB has microvia breakout, sequential lamination, or every-layer interconnects, then it will need the HDI structure named in the quote documents rather than merely an HDI designation.
The specific rules for spacing and trace widths are part of the PCB design-rule review; so they are not tied to the HDI fabrication package. They contribute to manufacturability but do not substitute for the build-up, microvia, and stackup data used to determine pricing to fabricate HDI boards.
Ultra HDI PCB Requirements Need Measurable Data
Ultra HDI designs will require clearly measurable data prior to quoting for fabrication. The term Ultra HDI typically refers to finer trace and space widths, often below 50 µm, smaller microvias, or SAP/mSAP build-up methods when those processes are specified. For quoting purposes, the quote documents must contain the target geometry and board configuration before Ultra HDI can be verified as an actual fabrication input.
Specifying trace and space widths, via size, pad geometry, number of layers, material system, and acceptance criteria makes the Ultra HDI label useful in comparing pricing.
When very fine geometry, non-traditional build-up, or unique process controls are driving the board constraints, Ultra HDI becomes a measurable fabrication input.
Assembly Requirements Outside Bare-Board Fabrication
Although HDI fabrication and PCB assembly are closely intertwined, they provide answers to different release questions. Via-in-pad designs enable dense package escape routes compared to traditional designs. Solder-joint inspection, component placement, functional test results, and assembly records require PCBA inspection and test evidence. The bare-board records support board release but do not necessarily approve the finished PCBA.
Board Types That Move Beyond HDI Fabrication
Some board types move beyond HDI fabrication because the main risk is not interconnect density. RF materials such as Rogers, PTFE, or other laminate materials may shift the question toward high-frequency PCB capability. Rigid-flex or flexible printed circuit (FPC) construction highlights bend areas, stiffener structure, coverlay material, and related flex details. Heavy copper may shift the focus toward current handling and copper balance within the PCB. Embedded components create their own build, inspection, and release questions.
Clear input data allows OEM teams to request the right manufacturing check. For HDI fabrication, focus on build-up structure, microvia data, stackup release, quote inputs, and bare-board records. Assembly, RF materials, rigid-flex construction, heavy copper, and embedded component work should have their own fabrication or assembly requests instead of a general HDI request.
Frequently Asked Questions
An HDI PCB is an HDI printed circuit board that can contain microvias, blind vias, buried vias, build-up layers, or via-in-pad structures. The build data is usually defined by a released stackup, drill information, and fabrication drawings for that PCB.
Ultra HDI PCB generally means a PCB that has finer geometry or denser interconnect needs than standard HDI. When quoting, trace and space, via size, pad geometry, layer stackup, and processing inputs are useful fields to have filled out; otherwise, Ultra HDI is a potential fabrication clarification point rather than a requirement.
Any layer in PCB refers to a structure where interconnects are not limited to only the outer build-up layers. In an HDI context, it means the fabricator must understand how the layers connect before pricing or confirming the build.
A bare PCB describes the board before components are assembled. An HDI PCB describes the interconnect structure of the board. A board can be both bare and HDI before assembly, so the two terms refer to different things.
Related Capabilities
HDI PCB fabrication is one aspect of an OEM’s advanced PCB decision. If another structure, material, or assembly requirement is included on the PCB, identify the primary manufacturing method early in the request so that quoting does not occur under an incorrect process.